Frequency divider system

ABSTRACT

A frequency divider circuit for providing a divided clock signal having a frequency that is an odd integer factor less than the frequency of an incoming system clock signal. The frequency divider includes a clock generator circuit coupled to a delay circuit which operates in an active and a reset phase to provide a divided clock signal from the system clock signal. In the active phase, the clock generator circuit drives the divided clock signal to a first logic state until a reset signal is received. The delay circuit then generates the reset signal at a predetermined number of system clock edges after the divided clock signal is driven to the first logic state. In the reset phase, both the clock generator circuit and the delay circuit are reset in response to the reset signal such that the clock generator circuit immediately drives the divided clock signal to a second logic state, and the delay circuit disables the reset signal within the predetermined number of system clock edges. The delay circuit maintains a 50% duty cycle for the divided clock signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to U.S. Provisional ApplicationNo. 60/372,425 filed on Apr. 16, 2002, the contents of which areincorporated herein, by reference, in their entirety.

FIELD OF THE INVENTION

This invention relates generally to frequency division techniques for RF(Radio Frequency) signals. More particularly, the present inventionrelates to a circuit for converting a system clock signal to a clocksignal having a reduced frequency.

BACKGROUND OF THE INVENTION

Most electronic devices require a clock signal to synchronize operationsof its internal components with each other. This clock signal iscommonly referred to as the system clock, and can be provided by acrystal oscillator having a fixed frequency. Telecommunication devicesalso require clock signals for transmission and reception of RF signalsin addition to a system clock.

Advances in circuit design and semiconductor manufacturing techniqueshave increased the maximum operating frequency of high performanceelectronic devices. For example, current Intel Pentium classmicroprocessors can run at a system clock frequency between 1 GHz and 2GHz.

Unfortunately, some components of an electronic device will only operateat a maximum frequency that is well below the desired system clockfrequency. Although different components will operate with differentclock frequencies, all the components of the electronic device mustoperate synchronously with each other. It is not possible to includeseparate crystal oscillators in the electronic device because it isimpractical to synchronize all the oscillators to the same system clockedges. Furthermore, the addition of more crystal oscillators increasesthe size of the electronic device, an undesirable attribute of portabledevices. Hence on chip frequency divider circuits are used to convertthe system clock signal to lower frequencies.

Generally, a frequency divider circuit removes a fixed number of cycles,or pulses, from the incoming system clock signal. For example, adivide-by-2 frequency divider that receives a 10 MHz signal will providea 5 MHz output. Therefore different components of the electronic devicecan operate at different speeds, but all synchronized to the systemclock and as a result, with each other. For wireless devices, theability to convert the system clock signal to different frequenciesenables its compatibility with regulatory requirements for differentfrequency bands and enables the device to do so in a cost effectivemanner, as well as enabling frequency translation of signals in systemswith multiple intermediate (IF) frequencies, synchronized calibration,shared clocks between different circuits.

Wireless devices with tri-band transceivers, such as GSM frequency bandsfor example, require a local oscillator signal in the RF receiverdown-conversion mixer and the RF transmitter up-conversion mixer inorder to receive and/or send RF signals. A divide by three factor of thesystem clock signal enables the use of a single local oscillator tosupport for example, the three GSM frequency bands. Frequency dividersof the art can divide the incoming frequency by any even or odd factor,and typically consists of a chain of flip-flop circuits arranged in aring such that its output is fed-back to its input. Traditionaldivide-by-3 or other odd numbered frequency dividers are not capable ofproducing a lowered frequency having a 50% duty cycle. A 50% duty cycleis highly desired in RF applications to reduce spurious outputs from thedevice as well as to reduce the sensitivity of the device to spuriousinputs. Furthermore, a 50% duty cycle is desired because when drivingmixers, the worst-case noise is seen when the mixer switches are both on(i.e. during the transition period). A 50% duty cycle minimizes theaverage noise and hence reduces the noise figure of the mixer.

Other frequency dividers require combinational logic between eachflip-flop stage which is difficult to implement in RF applications dueto the voltage headroom constraints and bandwidth limitations that canlimit performance of the device. Other solutions are too complex and arethus not cost effective implement.

It is therefore desirable to provide a frequency divider circuit thatprovides a reduced clock frequency having a 50% duty cycle which doesnot require the use of combinational logic between flip-flop stages, issimple and cost effective to implement.

SUMMARY OF THE INVENTION

It is an object of the present invention to obviate or mitigate at leastone disadvantage of previous frequency dividers, particularly those usedin mobile devices.

In a first aspect, the present invention provides a frequency dividerfor reducing the frequency of a clock signal by an odd numbered factorn, where n is an integer value. The frequency divider comprises a clockgenerator circuit for receiving the clock signal and for providing ann-divided clock signal having a first and second logic level. The clockgenerator circuit drives the n-divided clock signal from the first logiclevel to the second logic level in response to a reset signal. A clockdelay circuit activates the reset signal at n clock transitions afterreceiving the first logic level of the n-divided clock signal, anddeactivates the reset signal within n clock transitions after receivingthe second logic level of the divided clock signal. The clock generatorcircuit drives the n-divided clock signal from the second logic level tothe first logic level at n clock transitions after activation of thereset signal.

In presently preferred embodiments, the clock generator circuit includesa first resettable flip-flop having a data input connected to a supplyvoltage and a reset input for receiving the reset signal, a secondresettable flip-flop having a data input for receiving the divided clocksignal and a reset input for receiving the reset signal, the secondresettable flip-flop providing a delayed n-divided clock signal, and atleast one pair of serially connected non-resettable flip-flops receivingthe delayed n-divided clock signal from the second resettable flip-flopfor activating and deactivating the reset signal.

Other aspects and features of the present invention will become apparentto those ordinarily skilled in the art upon review of the followingdescription of specific embodiments of the invention in conjunction withthe accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will now be described, by way ofexample only, with reference to the attached Figures, wherein:

FIG. 1 shows a block diagram of an RF divider system according to anembodiment of the present invention;

FIG. 2 shows a block diagram of the divide-by-3 circuit block shown inFigure 1;

FIG. 3 shows a circuit diagram of the resettable flip-flop circuit ofFIG. 2;

FIG. 4 shows a circuit diagram of the non-resettable flip-flop circuitof FIG. 2; and,

FIG. 5 shows a sequence diagram illustrating the operation of thedivide-by-3 circuit of FIG. 2.

DETAILED DESCRIPTION

A frequency divider circuit for providing a divided clock signal havinga frequency that is a factor less than the frequency of an incomingsystem clock signal is disclosed. The frequency divider includes a clockgenerator circuit coupled to a delay circuit that operates in an activeand a reset phase to provide a divided clock signal from the systemclock signal. In the active phase, the clock generator circuit drivesthe divided clock signal to a first logic state until a reset signal isreceived. The delay circuit then generates the reset signal at a numberof system clock transitions after the divided clock signal is driven tothe first logic state. In the reset phase, the first two flip flops arereset only, the delay formed by the second two flip-flops does not haveany reset inputs, however, their inputs are reset to a logic ‘0’ twoclock cycles after the reset signal is asserted. The delay circuittherefore maintains a 50% duty cycle for the divided clock signal. Moreparticularly, the frequency divider according to embodiments of thepresent invention provides a clock signal that is divided by three, orany other odd divisions such as divide by (2*n+1) where n>=0 whilemaintaining a 50% duty cycle for the divided clock signal.

FIG. 1 is a block diagram of an RF divider system suitable for portablewireless devices. The RF divider system 100 receives a system clocksignal CLK and can selectively provide a divide-by-1, 2 or 3 clocksignal. Additionally, RF divider system 100 conserves power byactivating only the selected clock divider sub-circuit. RF dividersystem 100 includes a divide-by-3 sub-block, a divide-by-2 sub-block, adivide-by-1 sub-block, a decoder 102 and a bias circuit 104.

The divide-by-3 sub-block consists of a clock input buffer 106, adivide-by-3 circuit 108 and clock output buffer 110. The clock inputbuffer 106 receives the system clock CLK and provides a buffered CLKsignal to the divide-by-3 circuit 108. The divide-by-3 circuit 108generates a pre-buffered divided system clock signal having a frequencyequal to the system clock frequency divided by 3. The pre-buffereddivided system clock signal is buffered by clock output buffer 110 andappears on the o3 output terminal.

The divide-by-2 sub-block consists of a clock input buffer 112, adivide-by-2 circuit 114 and clock output buffer 116. The clock inputbuffer 112 receives the system clock CLK and provides a buffered CLKsignal to the divide-by-2 circuit 114. The divide-by-2 circuit 114generates a pre-buffered divided system clock signal having a frequencyequal to the system clock frequency divided by 2. The pre-buffereddivided system clock signal is buffered by clock output buffer 116 andappears on the o2 output terminal. For this particular embodiment, clockinput buffers 106 and 112 are identical, as are clock output buffers 110and 116.

The divide-by-1 sub-block consists of a clock input buffer 118 thatprovides a buffered CLK signal on the ot output terminal, and a clockinput buffer 120 that receives an external clock signal from its orinput terminal.

Decoder 102 receives selection signals div3, div2, div1 and Rx/Tx forcontrolling bias circuit 104. Bias circuit 104 receives a current signalIref and performs a sub-block select function, and based on the logicstates of the selection signals, drives Iref to power, or enable, one ofthe divide-by-3, divide-by-2 and divide-by-1 sub-blocks. In other words,bias circuit 104 selectively couples Iref to one of the aforementionedsub-blocks. This function is illustrated by the four individual linesextending from bias circuit 104 to their respective sub-blocks inFIG. 1. Accordingly, signals div3, div2, and div1 select the divisionfunction to enable, i.e. divide-by-3, divide-by-2 or divide-by-1,respectively. In the divide-by-1 case, the additional Rx/Tx signal isused to indicate which of ot and or, for transmitting and receivingrespectively, should be enabled. For example, if div3 is at a high logiclevel and all other selection signals are at a low logic level, decoder102 will control bias circuit 104 to selectively couple Iref to thedivide-by-3 sub-block consisting of buffers 106 and 110, and divide-by-3circuit 108.

Hence a system employing RF divider system 100 only requires a singleoscillator to provide a fixed system clock to provide divided clocksignals having one half or one third of the system clock frequency.Furthermore, the decoder 102 and bias circuit 104 help save power bykeeping unused sub-blocks inactive. Such a design helps conserve batterypower and extend the operation time of mobile devices.

The circuit implementations for clock input buffers 106 and 102, clockoutput buffers 110 and 116, decoder 102 and bias circuit 104 shown inFIG. 1 are well known in the art. Circuit details for the divide-by-3circuit 108 are shown in FIGS. 2 to 4.

FIG. 2 shows a block diagram of the divide-by-3 circuit 108 of FIG. 1.This circuit provides a divided clock signal having a frequency that isthree times less than the input system clock frequency, whilemaintaining a 50% duty cycle for the divided clock signal. In otherwords, the divided clock signal stays at a logic “1” level for aduration of three system clock transitions and a logic “0” level for aduration of three system clock transitions. The circuit does not requirecombinational logic between the flip-flops, and is simple to implement.Furthermore, the design is modular such that additional flip-flops canbe added to obtain other odd numbered divided system clock frequencieswithout further design overhead or complexity.

The divide-by-3 circuit 108 includes a clock generator circuit 130 and aclock delay circuit 132. The clock generator circuit consists of aresettable flip-flop 134 having the supply voltage VCC connected to itsDp data input, the supply voltage VEE or ground connected to its Dn datainput, the system clock signal CLK connected to its sampling clock inputCLK_S, and the inverted system clock signal CLK* connected to its resetclock input CLK_R. Those of skill in the art will appreciate that avoltage differential can established between the Dp and Dn inputs withanalog voltage levels instead of voltage supply voltage levels as shownin FIG. 2. Clock delay circuit 132 includes a resettable flip-flop 136,non-resettable flip-flop 138 and non-resettable flip-flop 140 connectedin series. The Dp and Dn inputs of flip-flop 136 are connected to the Qnand Qp outputs of flip-flop 134 respectively, while the CLK_S and CLK_Rinputs are connected to system clock signals CLK and CLK* respectively.Its R and R* inputs are connected to the Qp and Qn outputs respectivelyof non-resettable flip-flop 140.

The Dp and Dn inputs of flip-flop 138 are connected to the Qn and Qpoutputs of flip-flop 136 respectively, while the CLK_S input and latchclock input CLK_L are connected to system clock signals CLK* and CLKrespectively. The Dp and Dn inputs of flip-flop 140 are connected to theQp and Qn outputs of flip-flop 138 respectively, while the CLK_S andCLK_L inputs are connected to system clock signals CLK and CLK*respectively. The Qp and Qn outputs of non-resettable flip-flop 140 arefed back to the reset inputs R and R* of flip-flop 134 respectively. Thedivided clock signal can be tapped off of either node n1 or n2 becausethey provide a divided clock signal with a 50% duty cycle. However, itis preferable to use n2 as the divided clock signal because it haspassed through two gain stages and has less phase noise relative to noden1. This particular feature will be shown later with reference to thetiming diagram of FIG. 5. Therefore, the clock generator circuit caninclude both resettable flip-flops 134 and 136.

All the flip-flops of FIG. 2 are data inverting flow-through flip-flops,meaning that the logic states of each Dp and Dn input, when sampled, isimmediately inverted at its Qp and Qn outputs respectively. For theresettable flip-flops 134 and 136, a high logic state signal received atits CLK_S input while its R input is at the low logic state allows theflip-flop to sample its Dp and Dn inputs. Those of skill in the art willunderstand that R* is the inverted state of R, and CLK* is the invertedstate of CLK.

It should be noted that resettable flip-flops 134 and 136 are identicalflip-flop circuits, but the connections of the system clock inputsignals are reversed between flip-flops 134 and 136. Therefore,flip-flops 134 and 136 activate at different logic states of each CLKclock cycle. Non-resettable flip-flops 138 and 140 are identicalflip-flop circuits that also have reversed system clock input signalconnections between each other. Therefore flip-flops 134 and 138activate to sample input data at one logic state of each CLK clockcycle, while flip-flops 136 and 140 activate to sample input data at theother logic state of the same CLK clock cycle.

In general operation, the clock generator circuit 130 drives node n1 tothe logic “1” state, or level, in an active phase. The logic “1” stateof node n1 then propagates through delay circuit 132 and appears at noden4 three system clock transitions after node n1 was driven to the logic“1” state. Node n4 at the logic “1” state switches the divide-by-3circuit 108 to operate in a reset phase. Flip-flop 134 of clockgenerator circuit 130 is reset as is flip-flop 136 of delay circuit 132to drive nodes n1 and n2 to the logic “0” state. It is noted that due tothe reversed CLK and CLK* connections between flip-flops 134 and 136, n2is driven to the logic “0” state one CLK transition after n1 is drivento the logic “0” state. The logic “0” state of n2 propagates throughflip-flops 138 and 140 and appears at node n4 to switch the divide-by-3circuit 108 to operate in the active phase three CLK transitions aftern1 was driven to the logic “0” state. The clock generator circuit 130and clock delay circuit 132 then restart as previously described. Withthis circuit, nodes n1 and n2 remain at the logic “0” state for threeCLK transitions during the reset phase of operation.

The operation of divide by 3 circuit 108 is better understood followinga description of the resettable flip-flops 134 and 136 and thenon-resettable flip-flops 138 and 140. FIG. 3 is a circuit schematic ofresettable flip-flops 134 and 136. The input circuit includes a pair ofload devices, such as resistors 150 and 152, serially connected betweenVCC and the collector terminals of a pair of input transistors 154 and156 respectively. It is noted that all the transistors shown in thisschematic are n-type BJT transistors. The collector terminals of inputtransistors 154 and 156 are also connected to the complementary outputterminals Qp and Qn respectively. The base of input transistors 154 and156 are connected to data input terminals Dp and Dn respectively, whiletheir emitter terminals are connected in common to the collectorterminal of first mode transistor 158. A first latch circuit consistingof cross-coupled transistors 160 and 162 is coupled to output terminalsQp and Qn, and have their emitter terminals connected in common to thecollector terminal of second mode transistor 164. The emitter terminalsof mode transistors 158 and 164 are connected in common to the collectorterminal of first clock transistor 166, while the base of transistors158, 164 and 166 are connected to the R*, R and CLK_S input terminalsrespectively.

A second latch circuit consisting of cross-coupled transistors 168 and170 is coupled to output terminals Qp and Qn, and have their emitterterminals connected in common to the collector terminal of third modetransistor 172. The reset circuit includes first reset transistor 174having its collector connected to output terminal Qn and base connectedto the VCC supply, and second reset transistor 176 having its collectorconnected to output terminal Qp and base connected to a voltage dividercircuit. The emitter terminals of reset transistors 174 and 176 areconnected in common to the collector of fourth mode transistor 178, andthe emitter terminals of mode transistors 172 and 178 are connected incommon to the collector of second clock transistor 180. The base oftransistors 172, 178 and 180 are connected to the R*, R and CLK_R inputterminals respectively. The voltage divider includes resistors 182 and184 serially connected between VCC and ground. The emitter terminals oftransistors 166 and 180 are shown connected to current source Iref ofFIG. 1 for selective activation/deactivation of the circuit. Persons ofskill in the art will understand that the values of resistors 150, 152,182 and 184 can be optimized to maximize circuit performance.

Table 1 below summarizes the function of the resettable flip-flops 134and 136 according to the logic states of the CLK and R signals. TABLE 1CLK_S CLK_R R R* Function 1 0 0 1 Sample Dp and Dn inputs 0 1 0 1 Latchsampled Dp & Dn inputs 0 1 1 0 Reset Qn to “0” state and Qp to “1” state1 0 1 0 Latch reset states

An example of the operation of resettable flip-flops 134 and 136 nowfollows with reference to FIG. 3. As shown in Table 1, the input circuitof the resettable flip-flops 134 and 136 only sample data on its Dp andDn input terminals when the R* and CLK_S input terminals receive a logic“1” voltage level, such as VCC supply voltage for example, to turn ontransistors 158 and 166. Thus if input terminals Dp and Dn receive logic“1” and “0” voltage levels respectively, then Qp is driven towards thelogic “0” voltage level while Qn remains at the logic “1” voltage level.When the CLK_S input terminal transitions to the logic “0” level to turnoff transistor 166, the CLK_R input terminal correspondingly transitionsto the logic “1” level to turn on transistor 180. Since transistor 172is also turned on by R* at the logic “1” level, the second latch circuitlatches the logic states of the Qp and Qn output terminals at the logic“0” and “1” levels respectively. When R* changes to the logic “0” level,R changes to the logic “1” level to turn on transistors 164 and 178.When the CLK_R input terminal is at the logic “1” level, the resetcircuit is turned on and the output terminal Qn is driven towards thelogic “0” level while Qp remains at the logic “1” level. In thisparticular embodiment, the reset circuit drives the preset logic statesof “0” and “1” onto the Qn and Qp output terminals respectively. Thoseof skill in the art will appreciate that the values of resistors 182 and184 are selected such that the voltage level of Qp is maintained at ahigher voltage level than that of Qn. When the CLK_S input terminal isat the logic “1” level, transistor 164 is turned on and the first latchcircuit latches the logic states of the Qp and Qn output terminals atthe logic “1” and “0” levels respectively. In summary, while the R inputterminal is at the logic “0” level the resettable flip-flop circuitalternately turns on the input circuit and the second latch circuit inaccordance with the logic transitions of the system clock signal.Accordingly, while the R input terminal is at the logic “1” level theresettable flip-flop circuit alternately turns on the reset circuit andthe first latch circuit in accordance with the logic transitions of thesystem clock signal.

FIG. 4 is a circuit schematic of non-resettable flip-flops 138 and 140.The non-resettable flip-flop circuit shown in FIG. 4 is similar inconfiguration and function to the schematic of the resettable flip-flopcircuit shown in FIG. 3. The input circuit includes a pair of loadresistors 190 and 192 serially connected between VCC and the collectorterminals of a pair of differential input transistors 194 and 196respectively. It is noted that all the transistors shown in thisschematic are n-type BJT transistors. The collector terminals of inputtransistors 194 and 196 are also connected to the complementary outputterminals Qp and Qn respectively. The base of input transistors 194 and196 are connected to data input terminals Dp and Dn respectively, whiletheir common emitter terminals are connected in common to the collectorterminal of first clock transistor 198. A latch circuit consisting ofcross-coupled transistors 200 and 202 is coupled to output terminals Qpand Qn, and have their emitter terminals connected in common to thecollector terminal of second clock transistor 204. The emitters of clocktransistors 198 and 204 are connected to current source Iref, forselective activation/deactivation as described above, while their basesare connected to the CLK_S and CLK_L terminals respectively.

The circuit of FIG. 4 functions in a similar fashion to the circuit ofFIG. 3. The input circuit is turned on to sample data appearing on itsDp and Dn input terminals when the CLK_S input terminal is at the logic“1” level, and the latch circuit latches the Qp and Qn logic levels whenCLK_L is at the logic “1” level. Because the reset transistors are notused in this circuit, this particular circuit does not operate in areset phase, but will alternately sample and latch data appearing on itsDp and Dn input terminals in accordance with the logic transitions ofthe system clock signal.

A detailed description of the operation of the divide-by-3 circuit 108of FIG. 2 follows with reference to the timing diagram of FIG. 5. Thetiming diagram of FIG. 5 shows the traces for CLK, CLK*, nodes n1, n2,n3 and n4 from the block diagram of FIG. 2. The following descriptionfollows seven CLK transitions which are labelled at the bottom of thetiming diagram. Transition arrows indicate the events that trigger atransition of another signal trace. It is assumed that the divide-by-3circuit 108 starts in the reset phase of operation.

At the beginning of clock transition 1, node n1 drops to the logic “0”level, or the low logic level at first transition arrow 300 because thereset circuit of flip-flop 134 is turned on while node n4 and CLK are atthe logic “1”, or high logic level. As previously discussed for thecircuit schematic of FIG. 3, Qp and Qn (node n1) are driven to the highand low logic levels respectively when its reset circuit is turned on.

At the beginning of clock transition 2 node n2 drops to the low logiclevel as indicated by second transition arrow 302, because the resetcircuit of flip-flop 136 is turned on when CLK* and node n4 are at thehigh logic level. Note that the first latch circuit of flip-flop 134latches its Qp and Qn logic states when CLK* is at the high logic level.

Shortly after node n2 drops to the low logic level in clock transition2, node n3 drops to the low logic level at third transition arrow 304because the input circuit of flip-flop 138 is turned on at the same timethe reset circuit of flip-flop 136 is turned on while CLK* is at thehigh logic level. The short delay between n2 and n3 dropping to the lowlogic levels is due to the inherent delay of the input circuittransistors of flip flop 138.

At the beginning of clock transition 3 node n4 drops to the low logiclevel at fourth transition arrow 306 because the input circuit offlip-flop 140 is turned on while CLK is at the high logic level tosample the Qp and Qn outputs of flip-flop 138. Note that the latchcircuit of flip-flop 138 latches its Qp and Qn logic states when CLK isat the high logic level in clock transition 3. Although the Qn output offlip-flop 140 is at the high logic level (complement of n4), the inputcircuit of flip-flop 134 does not turn on because CLK* is at the lowlogic level in clock transition 3. Therefore the outputs of flip-flop134 do not change.

At the beginning of clock transition 4 node n1 rises to the high logiclevel because the input circuit of flip-flop 134 is turned on to samplethe logic level of node n4 as indicted by fifth transition arrow 308.Sixth transition arrow 310 indicates that the input circuit is turned onwhen CLK* is at the high logic level. Divide-by-3 circuit 180 is nowswitched to the active phase of operation.

Node n2 rises to the high logic level in clock transition 5 when theinput circuit of flip-flop 136 turns on to sample the logic level ofnode n1 when CLK is at the high logic level, as indicated by seventhtransition arrow 312. Note that the Qn output of flip-flop 134 isconnected to the Dp input of flip-flop 136, hence the Qn output offlip-flop 136 (node n2) has a logic level that follows its Dp input.

Node n3 rises to the high logic level in clock transition 6 when theinput circuit of flip-flop 138 turns on to sample the logic level ofnode n2 when CLK* is at the high logic level, as indicated by eighthtransition arrow 314. Note that the Qn output of flip-flop 136 isconnected to the Dp input of flip-flop 138, hence the Qn output offlip-flop 138 (node n3) has a logic level that follows its Dp input.

In clock transition 7 node n4 rises to the high logic level when theinput circuit of flip-flop 140 turns on to sample the logic level ofnode n3 when CLK is at the high logic level, as indicated by ninthtransition arrow 316. Furthermore since node n4 is now at the high logiclevel in clock transition 7, the reset circuit of flip-flop 134 isturned on while CLK is at the high logic level as indicated by tenthtransition arrow 318, causing node n1 to be driven to the low logiclevel. The reset phase of operation begins in clock transition 7 as itdid in clock transition 1.

Looking at the signal trace for node nil, after n1 falls to the lowlogic level in clock transition 1, it then rises to the high logic levelthree clock transitions later in clock transition 4. After nil rises thehigh logic level in clock transition 4, it then falls to the low logiclevel three clock translations later in clock transition 7. Thus node n1alternately stays at the high logic level and the low logic level for aduration of three clock transitions.

From the timing diagram, it is apparent that the divided clock signalhaving one third the frequency of the system clock CLK can be obtainedthrough nodes n1 or n2. Furthermore, the divided clock signal obtainedfrom nodes n1 or n2 have a 50% duty cycle which is greatly desired in RFapplications.

The illustrated embodiments of the present invention show that a dividedclock signal having a frequency equal to the input system clockfrequency divided by a factor of three can be generated. However, inalternate embodiments of the present invention, divided clock signalshaving a frequency equal to the input system clock frequency divided byany odd factor can be generated. To divide the input system clock byfive, two additional non-resettable flip-flops can be added to the clockdelay circuit 132 of divide-by-3 circuit 108 in FIG. 2. Morespecifically the two additional non-resettable flip-flops, eachidentical to flip-flop 138, are inserted between flip-flop 136 and 138.The first additional flip-flop has its Dp and Dn inputs connected to theQn and Qp outputs respectively of flip-flop 136 and has its CLK_S andCLK_L inputs connected to CLK* and CLK respectively. The secondadditional flip-flop has its Dp and Dn inputs connected to the Qp and Qnoutputs respectively of the first additional flip-flop and has its CLK_Sand CLK_L inputs connected to CLK and CLK* respectively. The Qp and Qnoutputs of the second additional flip-flop are then connected to the Dpand Dn inputs respectively of flip-flop 138. Alternatively, the twoadditional resettable flip-flops can be appended to flip-flop 140instead. Therefore pairs of non-resettable flip-flops can be added tothe clock delay circuit 132 to divide the input clock signal by any oddinteger number.

Although the embodiments of the present invention are exemplified usingBJT technology, alternate embodiments can be implemented in CMOStechnology or any suitable transistor technology, and alternate loaddevices such as diode connected transistors for example, are appropriatesubstitutes for load resistors.

The above-described embodiments of the present invention are intended tobe examples only. Alterations, modifications and variations may beeffected to the particular embodiments by those of skill in the artwithout departing from the scope of the invention, which is definedsolely by the claims appended hereto.

1. A frequency divider for reducing the frequency of a clock signal byan odd numbered factor n, where n is an integer value, comprising: aclock generator circuit for receiving the clock signal and for providingan n-divided clock signal having a first and second logic level, theclock generator circuit driving the n-divided clock signal from thefirst logic level to the second logic level in response to a resetsignal; and, a clock delay circuit for activating the reset signal at nclock transitions after receiving the first logic level of the n-dividedclock signal, and for deactivating the reset signal within n clocktransitions after receiving the second logic level of the divided clocksignal, the clock generator circuit driving the n-divided clock signalfrom the second logic level to the first logic level at n clocktransitions after activation of the reset signal.
 2. The frequencydivider of claim 1, wherein the clock generator circuit includes a firstresettable flip-flop having a data input connected to a supply voltageand a reset input for receiving the reset signal.
 3. The frequencydivider of claim 2, wherein the clock delay circuit includes a secondresettable flip-flop having a data input for receiving the divided clocksignal and a reset input for receiving the reset signal, the secondresettable flip-flop providing a delayed n-divided clock signal, and atleast one pair of serially connected non-resettable flip-flops receivingthe delayed n-divided clock signal from the second resettable flip-flopfor activating and deactivating the reset signal.
 4. The frequencydivider of claim 3, wherein the first resettable flip-flop and the firstnon-resettable flip-flop of each pair of non-resettable flip-flopsreceive the clock signal, and the second resettable flip-flop and thesecond non-resettable flip-flop of each pair of non-resettableflip-flops receive an inverted clock signal.
 5. The frequency divider ofclaim 4, wherein an output of the at least one serially connected pairof non-resettable flip-flops are connected to the reset inputs of thefirst and second resettable flip-flops.
 6. The frequency divider ofclaim 5, wherein the first resettable flip-flop, the second resettableflip-flop, and the pair of non-resettable flip-flops are data invertingflow through flip-flops.
 7. The frequency divider of claim 4, whereineach resettable flip-flop includes an input circuit receiving a pair ofinput signals in response to a first transition of the clock signal forinverting a logic level of the input signals at complementary outputterminals during an active phase of operation; an input latch circuitfor latching the logic states of the complementary output terminals inresponse to a second transition of the clock signal during the activephase of operation; a reset circuit for driving the complementary outputterminals to preset logic states in response to the second transition ofthe clock signal during a reset phase of operation; and, a reset latchcircuit for latching the preset logic states of the complementary outputterminals in response to the first transition of the clock signal duringthe reset phase of operation.
 8. The frequency divider of claim 1,wherein the n clock transitions include transitions in both positive andnegative directions.
 9. The frequency divider of claim 1, wherein eachresettable flip-flop includes a first load device connected between VCCand one of the complementary output terminals, a second load deviceconnected between VCC and an other of the complementary outputterminals, a first input transistor having a collector connected to theone of the complementary output terminals and a base for receiving oneof the pair of input signals, a second input transistor having acollector connected to the other of the complementary output terminalsand a base for receiving an other of the pair of input signals, theemitters of the first and second input transistors being connected toeach other, a first mode transistor having a collector connected to theemitters of the first and second input transistors and a base forreceiving the reset signal, a first pair of cross-coupled transistorshaving collectors connected to the complementary output terminals, asecond mode transistor having a collector connected to the emitters ofthe first pair of cross-coupled transistors and a base for receiving aninverted reset signal, the emitters of the first and second phasetransistors being connected to each other, a first clock transistorhaving a collector connected to the emitters of the first and secondmode transistors, an emitter connected to VEE, and a base for receivingthe clock signal, a second pair of cross-coupled transistors havingcollectors connected to the complementary output terminals, a third modetransistor having a collector connected to the emitters of the secondpair of cross-coupled transistors and a base for receiving the resetsignal, a first reset transistor having a collector connected to the oneof the complementary output terminals and a base connected to VCC, asecond reset transistor having a collector connected to the other of thecomplementary output terminals and a base for receiving a referencevoltage, the emitters of the first and second reset transistors beingconnected to each other, a fourth mode transistor having a collectorconnected to the emitters of the first and second reset transistors anda base for receiving the inverted reset signal, and a second clocktransistor having a collector connected to the emitters of the third andfourth phase transistors, an emitter connected to VEE, and a base forreceiving an inverted clock signal.
 10. A frequency divider for reducingthe frequency of a clock signal by a factor of three, comprising: aclock generator circuit having a data input for receiving a supplyvoltage, a clock input for receiving the clock signal and a reset inputfor receiving a reset signal, for providing a divide-by-3 clock signalhaving a first and second logic level from an output terminal, the clockgenerator circuit driving the divide-by-3 clock signal from the firstlogic level to the second logic level in response to the reset signal;first, second and third serially connected clock delay flip-flops eachreceiving the clock signal for receiving the divide-by-3 clock signaland for activating the reset signal at three clock transitions afterreceiving the first logic level of the divide-by-3 clock signal, and fordeactivating the reset signal within three clock transitions afterreceiving the second logic level of the divide-by-3 clock signal, theclock generator circuit driving the divide-by-3 clock signal from thesecond logic level to the first logic level at three clock transitionsafter activation of the reset signal.
 11. The frequency divider of claim10, wherein the clock generator circuit includes a resettable flip-flop.12. The frequency divider of claim 11, wherein the first clock delayflip-flop is a resettable flip-flop having a reset input.
 13. Thefrequency divider of claim 12, wherein the second and third clock delayflip-flops are non-resettable flip-flops.
 14. The frequency divider ofclaim 13, wherein the clock generator circuit and the second clock delayflip-flop receives the clock signal, and the first clock delay flip-flopand the third clock delay flip-flop receives an inverted clock signal.15. The frequency divider of claim 14, wherein an output of the thirdclock delay flip-flop is connected to the reset inputs of the clockgenerator circuit and the first clock delay flip-flop.
 16. The frequencydivider of claim 11, wherein the clock generator circuit, the first,second and third clock delay flip-flops are data inverting flow throughflip-flops.
 17. An RF divider system for providing divided clock signalsfrom a clock signal comprising: a divide-by-3 sub-block receiving theclock signal for providing a divide-by-3 clock signal; a divide-by-2sub-block receiving the clock signal for providing a divide-by-2 clocksignal; a divide-by-1 sub-block receiving the clock signal for providinga divide-by-1 clock signal; a bias circuit for selectively coupling acurrent signal to one of the divide-by-3 sub-block, the divide-by-2sub-block and the divide-by-1 sub-block; and, a decoder circuitreceiving sub-block selection signals for controlling the bias circuit.18. The RF divider system of claim 17, wherein the divide-by-3 sub-blockincludes a clock input buffer for buffering the clock signal; adivide-by-3 circuit for generating a pre-buffered divide-by-3 clocksignal from the buffered clock signal; and, a clock output buffer forbuffering the pre-buffered divide-by-3 clock signal to provide thedivide-by-3 clock signal.
 19. The RF divider system of claim 18, whereinthe divide-by-3 circuit includes a clock generator circuit for receivingthe buffered clock signal and for providing the pre-buffered divide-by-3clock signal having a first and second logic level, the clock generatorcircuit driving the pre-buffered divide-by-3 clock signal from the firstlogic level to the second logic level in response to a reset signal;and, a clock delay circuit for activating the reset signal at threeclock transitions after receiving the first logic level of thepre-buffered divide-by-3 clock signal, and for deactivating the resetsignal within three clock transitions after receiving the second logiclevel of the pre-buffered divide-by-3 clock signal, the clock generatorcircuit driving the pre-buffered divide-by-3 clock signal from thesecond logic level to the first logic level at three clock transitionsafter activation of the reset signal.
 20. A method for generating ann-divided clock signal having a 50% duty cycle at an output of a clockgenerator from a clock signal, where n is an integer value, comprising:a) switching the clock generator to an active phase of operation; b)driving the output of the clock generator to a first logic level in theactive phase of operation; c) activating a reset signal for switchingthe clock generator circuit to a reset phase of operation at n clocksignal transitions after the output of the clock generator is driven tothe first logic level; d) driving the output of the clock generator to asecond logic level in the reset phase of operation; and, e) deactivatingthe reset signal for switching the clock generator to the active phaseof operation at n clock signal transitions after the output of the clockgenerator is driven to the second logic level.
 21. The method forgenerating an n-divided clock signal of claim 20, wherein the step ofdriving the output of the clock generator to the first logic levelincludes delaying activation of the reset signal until the nth clocksignal transition after the n-divided clock signal is driven to thefirst logic level.
 22. The method for generating an n-divided clocksignal of claim 20, wherein the first logic level of the divided clocksignal is a high logic level and the second logic level of the dividedclock signal is a low logic level.
 23. The method for generating ann-divided clock signal of claim 20, wherein the step of deactivating thereset signal includes delaying deactivation of the reset signal untiln−1 system clock signal transitions after the n-divided clock signal isdriven to the second logic level.
 24. A resettable flip-flop circuitresponsive to a clock signal comprising: an input circuit receiving apair of input signals in response to a first transition of the clocksignal for inverting a logic level of the input signals at complementaryoutput terminals during an active phase of operation; an input latchcircuit for latching the logic states of the complementary outputterminals in response to a second transition of the clock signal duringthe active phase of operation; a reset circuit for driving thecomplementary output terminals to preset logic states in response to thesecond transition of the clock signal during a reset phase of operation;and, a reset latch circuit for latching the preset logic states of thecomplementary output terminals in response to the first transition ofthe clock signal during the reset phase of operation.
 25. The resettableflip-flop circuit of claim 24, wherein the input circuit includes adifferential pair of transistors for receiving the pair of inputsignals, a load circuit for coupling a first supply voltage to each ofthe differential pair of transistors and to each of the complementaryoutput terminals, and a pair of control transistors serially connectedbetween the differential pair of transistors and a second supply voltagefor receiving a reset signal and the clock signal.
 26. The resettableflip-flop circuit of claim 24, wherein the input latch circuit includesa pair of cross-coupled transistors and a pair of control transistorsserially connected between the cross-coupled transistors and a secondsupply voltage for receiving a reset signal and the clock signal. 27.The resettable flip-flop circuit of claim 24, wherein the reset latchcircuit includes a pair of cross-coupled transistors and a pair ofcontrol transistors serially connected between the cross-coupledtransistors and a second supply voltage for receiving a reset signal andthe clock signal.
 28. The resettable flip-flop circuit of claim 24,wherein the reset circuit includes a first reset transistor connected toone of the complementary output terminals, and having a control terminalconnected to a power supply voltage, a second reset transistor connectedto the other of the complementary output terminals and the first resettransistor, and having a control terminal biased to a reference voltagelevel, and a pair of control transistors serially connected between thecommon first and second transistor terminals and a second supplyvoltage, for receiving a reset signal and the clock signal.
 29. Theresettable flip-flop circuit of claim 28, wherein the reference voltagelevel is generated by a voltage divider circuit.